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RF2861
0
RoHS Compliant & Pb-Free Product Typical Applications * CDMA/JCDMA Cellular Systems * CDMA450 Handsets/Data Cards * AMPS Cellular Systems Product Description
-A-
CDMA LOW NOISE AMPLIFIER/MIXER 900MHz DOWNCONVERTER
* General Purpose LNA and Downconverter * Commercial and Consumer Systems * Portable Battery-Powered Equipment
0.10 C A
0.05 C
3.00
2 PLCS
The RF2861 is a receiver front-end for CDMA cellular applications, including JCDMA and CDMA450. It is designed to amplify and downconvert RF signals, using a three gain state LNA to obtain 17dB of stepped gain control. Features include digital control of LNA gain and power down mode, along with an integrated TX LO buffer amplifier. Another feature of the chip is adjustable IIP3 of the LNA and mixer using off-chip current setting resistors to allow for minimum DC current consumption. Noise figure, IIP3, and other specs are designed to be compatible with the TIA/EIA 98D standard for CDMA cellular communications. The IC is manufactured on an advanced Silicon Germanium Bi-CMOS process and is in a 3mmx3mm, 16-pin, QFN.
1.50 TYP
2 PLCS
0.90 0.85 0.70 0.65
0.10 C B
0.05 0.00
3.00 12 MAX
2 PLCS
0.10 C B
-B-
1.37 TYP
2 PLCS
-CDimensions in mm.
SEATING PLANE
2.75 SQ 0.60 0.24 TYP
0.10 C A 0.10 M C A B
0.30 0.18
2
NOTES: 1. Shaded lead is pin 1. 2 Dimension applies to plated terminal: to be measured between 0.20 mm and 0.25 mm from terminal end.
PIN 1 ID R.20
1.65 SQ. 1.35 0.50 0.30
0.50
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
Package Style: QFN, 16-Pin, 3x3
Features * 3mmx3mm LNA/Mixer Solution * Adjustable LNA and Mixer Current/IIP3
TX BUFF ENABLE
ENABLE
LO OUT
VCC
* Meets IMD Tests with Three Gain States/Two Logic Control Pins
12 LO IN 11 GND 10 IF OUT9 IF OUT+
16 G2 1 LNA IN 2 LNA EMITTER 3 LNA OUT 4 5 ISET2
15
14
13
* Integrated TX LO Buffer Amplifier * Full ESD Protection on all Pins
Ordering Information
RF2861 RF2861PCBA-41X CDMA Low Noise Amplifier/Mixer 900MHz Downconverter Fully Assembled Evaluation Board Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
6 ISET1
7 G1
8 MIX IN
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Rev A3 050902
8-1
RF2861
Absolute Maximum Ratings Parameter
Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature
Rating
-0.5 to +5.0 +6 -40 to +85 -40 to +150
Unit
VDC dBm C C
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall
RF Frequency Range IF Frequency Range
Min.
Specification Typ. Max.
460 to 900
Unit
MHz MHz V V V
Condition
T = 25C, VCC =2.75V
0.1 2.65 1.8 2.75
400 3.15 0.4
Power Supply
Supply Voltage Logic High Logic Low
Cellular CDMA Band JCDMA Band LNA (High Gain)
Gain Noise Figure Input IP3 Current Isolation 13.0 9.0 18.5 4.0 7.0 12.5 -4.0 +25.0 1.0 9.0 +6.0 36 10.5 7.5 +8.5 12.0 8.0 -2.5 2.5 +27.0 0 -1.0 4.0 6.0 3.0 9.0 3.5 7.0 3.3 14.5 1.1 11.0 7.0 16.0 1.3 dB dB dBm mA dB dB dB dBm mA dB dB dB dBm mA dB
Freq=869MHz to 894MHz Freq=832MHz to 870MHz LNA 50 match
LNA (Mid Gain)
Gain Noise Figure Input IP3 Current Isolation
LNA (Low Gain)
Gain Noise Figure Input IP3 Current Isolation
Mixer - CDMA/JCDMA/FM
Gain Noise Figure Input IP3 LO to RF Isolation dB dB dBm dB dB dB dBm dB 30 mA
IF tune set for nominal mixer gain, high IIP3 184MHz IF (NF=8.3dB, 85MHz IF) LO=1064MHz IF tune set for high mixer gain, nominal IIP3 184MHz IF (NF=8.3dB, 85MHz IF) LO=1064MHz TX LO Buffer Off
Mixer - CDMA/JCDMA/FM
Gain Noise Figure Input IP3 LO to RF Isolation 13.0 7.5 +6.5 36 25
Cascade - High Gain
Current
8-2
Rev A3 050902
RF2861
Parameter
Cellular CDMA Band JCDMA Band, cont'd Other
LO-IF Isolation RF-IF Isolation LNA Out to Mixer In Isolation LO-LNA In Isolation, Any State 30 45 45 40 1 dB dB dB dB pF LO=1064MHz
Min.
Specification Typ. Max.
Unit
Condition
LO=1064MHz G1, G2, ENABLE, TX BUFF ENABLE
Control Lines
Input Capacitance
Local Oscillator Input
Cellular - CDMA or FM Input Power Input Frequency -10 685 1053 784 954 -10 722 942 -10 505 -4 0 710 1078 809 979 0 760 980 0 575 dBm MHz MHz MHz MHz dBm MHz MHz dBm MHz
IF=184MHz IF=184MHz IF=85MHz IF=85MHz
Cellular - JCDMA Input Power Input Frequency CDMA450 Input Power Input Frequency
-4
IF=110MHz IF=110MHz
-4
CDMA450 Band LNA (High Gain)
Gain Noise Figure Input IP3 Current Isolation 15.0 1.4 +8.0 8.7 18.5 +2.5 2.9 +14.0 4.7 12.5 -4.0 4.0 +25.0 0 1.0 12.0 7.5 5.0 36 25 40 40 30 dB dB dBm mA dB dB dB dBm mA dB dB dB dBm mA dB
IF=85MHz Freq=463MHz to 467MHz LNA 50 match
LNA (Mid Gain)
Gain Noise Figure Input IP3 Current Isolation
LNA (Low Gain)
Gain Noise Figure Input IP3 Current Isolation
Mixer
Gain Noise Figure Input IP3 LO to RF Isolation dB dB dBm dB dB dB dB dB
IF tune set for high mixer gain, nominal IIP3
LO=549MHz LO=549MHz
CDMA450 Isolation
LO-IF Isolation RF-IF Isolation LNA Out to Mixer In Isolation LO-LNA In Isolation, Any State
LO=549MHz
Rev A3 050902
8-3
RF2861
Parameter
TX (Local Oscillator) Buffer Output
Cellular - CDMA or FM Output Power Output Frequency -7 685 1053 784 954 -5 -3 710 1078 809 979 dBm MHz MHz MHz MHz mA dBm MHz MHz mA dBm MHz mA Single-ended 50 load IF=184MHz IF=184MHz IF=85MHz IF=85MHz
Min.
Specification Typ. Max.
Unit
Condition
Current Consumption Cellular - JCDMA Output Power Output Frequency Current Consumption CDMA450 Output Power Output Frequency Current Consumption
2 -7 722 942 -5 -3 760 980
Single-ended 50 load IF=110MHz IF=110MHz
2 -7 505 -5 2 -3 575
Single-ended 50 load IF=85MHz
8-4
Rev A3 050902
RF2861
Gain Control Logic Table
Gain State ENABLE G1 G2 High Gain 1 0 0 Mid Gain 1 1 0 Low Gain 1 1 1 Low Gain (alternate) 1 0 1 NOTES: All IDC current numbers include bias circuitry current of 1.5mA to 2.0mA (dependent on mode). TX Buffer On: Add 2mA to total current.
Cell Band Cascaded Performance High Mixer Gain Nominal IIP3 (Typical Values for VCC =2.75V) NOTE: All total current numbers include bias circuitry current of 1.5mA to 2.0mA (dependent on mode).
Parameter LNA (High Gain) CELL CDMA LNA (Mid Gain) 16.5 6.3 +2.0 21.5 LNA (Low Gain) 8.0 12.5 +11.4 18.0
Cascaded: Gain (dB) 25.0 Noise Figure (dB) 2.1 Input IP3 (dBm) -5.6 Total Current (mA) 25.0 NOTE: Assumes 2.5dB image filter insertion loss. The TX Buffer is off.
Cell Band Cascaded Performance Nominal Mixer Gain High IIP3 (Typical Values for VCC =2.75V)
Parameter LNA (High Gain) CELL CDMA LNA (Mid Gain) 14.0 6.3 +3.5 21.5 LNA (Low Gain) 5.5 12.5 +13.3 18.0 Cascaded: Gain (dB) 22.5 Noise Figure (dB) 2.1 Input IP3 (dBm) -3.7 Total Current (mA) 25.0 NOTE: Assumes 2.5dB image filter insertion loss. The TX Buffer is off.
CDMA450 Band Cascaded Performance (Typical Values for VCC =2.75V)
Parameter LNA (High Gain) CDMA450 LNA (Mid Gain) 12.0 8.5 +4.5 25 LNA (Low Gain) 5.5 14.0 +11.3 21 Cascaded: Gain (dB) 24.5 Noise Figure (dB) 2.2 Input IP3 (dBm) -7.6 Total Current (mA) 29.5 NOTE: Assumes 2.5dB image filter insertion loss. The TX Buffer is off.
Rev A3 050902
8-5
RF2861
Pin 1 Function G2 Type Description DI Gain control logic input. See logic control table. Interface Schematic
G2
2
LNA IN
AI
Cellular LNA input.
LNA IN
VCC LNA OUT
LNA EMITTER
3 4 5 6 7
LNA EMITTER LNA OUT ISET2 ISET1 G1
AO AO AO AO DI
Cellular LNA emitter. A small inductor connects this pin to ground. Cellular LNA gain can be adjusted by the inductance. Cellular LNA output. Simple external L-C components required for matching and VCC supply. An external resistor connected to this pin sets the current of the mixer. Increasing resistance decreases current. An external resistor connected to this pin sets the current of the LNA. Increasing resistance decreases current. Gain control logic input. See logic control table.
See pin 2. See pin 2.
G1
8
MIX IN
AI
Cellular mixer RF single-end input.
MIX IN
9
IF OUT+
AO
CDMA IF output. Open collector.
IF OUT+
IF OUT-
10 11 12
IF OUTGND LO IN
AO P AI
CDMA IF output. Open collector. Ground. LO single-end input. Matched to 50.
See pin 9.
LO IN 70
13 14 15
VCC LO OUT TX BUFF ENABLE ENABLE
P AO DI
LO amplifier VCC external bypass capacitor may be required. LO output. Internal DC block. Drives 50. Logic input. High enables TX LO output buffer amplifiers.
TX BUFF ENABLE
16
DI
Logic input. Low level powers down the IC.
ENABLE
Pkg Base
Legend:
GND
Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. DI=Digital Input from Baseband Chip AI=Analog Input AO=Analog Output P=VCC or GND
P
8-6
Rev A3 050902
RF2861
Application Schematic Differential IF Matching
G2 ENABLE TX BUFF ENABLE LO OUT V CC
2.2 nH
33 nF 0603 Wire-wound Inductors 33 nF CELL LNA IN 33 nH 1 2 1.2 nH 3 33 nF 10 nH 4 V CC 5 6 7 G1 3.9 pF 9.1 k RF Saw
1 4 GND OUT GND
16
15
14
13 12 11 10 9 8 C1 R1 L2 V CC L1 L3 33 nF DNI C3 IF Saw
5 4 9 10
LO IN
IFIF+
C2
20 k
33 nF C1 R1 85 MHz IF (LO 22 pF 2.7 k FREQ=965 MHz) 184 MHz IF (LO 5.0 pF 2.7 k FREQ=1064 MHz) L1 72 nH 55 nH L2 72 nH 55 nH C2 C3 L3 220 nH 43 nH IF SAW FILTER SAWTEK 855845 EPCOS B4955 5.1 pF 5.1 pF 10 pF 10 pF
2 GND GND 3 6
IN
DNI 22 nH
5
Rev A3 050902
8-7
RF2861
Application Schematic Single-End Matching
G2 ENABLE TX BUFF ENABLE LO OUT
2.2 nH
33 nF
VCC
33 nF CELL LNA IN 33 nH 1 2 1.2 nH 3 33 nF 10 nH 4 VCC
16
15
14
13 12 11 C1 10 9 L1 VCC 33 nF IF Saw
5 4 9 10
LO IN
IFIF+
C2
C3
R1
L2
5
6
7 G1
8 C4 C5 L3
3.9 pF 9.1 k RF Saw 2
IN 1 4 GND OUT GND GND GND 3 6
20 k 85 MHz IF (LO FREQ=965 MHz) 33 nF + 184 MHz IF (LO FREQ=1064 MHz)
C1 (pF) 43 13
C2 (pF) 43 13
C3 DNI DNI
R1 (k) 2.7 2.7
L1 (nH) 72 55
L2 (nH) 72 55
C4 (pF) 5.1 10
C5 DNI DNI
L3 (nH) 220 43
IF SAW FILTER SAWTEK 855845 EPCOS B4955
5
22 nH
DNI
8-8
Rev A3 050902
RF2861
Application Schematic Single-End Matching CDMA450 Band
G2 ENABLE TX BUFF ENABLE LO OUT
2.2 nH
33 nF
VCC
33 nF CELL LNA IN 33 nH 1 2 5.6 nH 3 100 pF 27 nH 4 VCC
16
15
14
13 12 11 C1* 10 9
0603 Wire-wound Inductors LO IN
IF Saw L1* VCC 33 nF
5 4 9 10
IFIF+
C2*
C3*
R1*
L2*
5
6
7 G1
8 C4* C5* L3*
27 pF 6.8 k RF Saw 2
IN 1 4 GND OUT GND GND GND 3 6
*Values determined by choice of IF SAW. 22 k
+ +
33 nF
5
2.2 pF
33 nH
Rev A3 050902
8-9
RF2861
Evaluation Board Schematic
ENABLE TX BUFF ENABLE C46 33 nF C54 33 nF J6 LO OUT VCC P1 P1-1 + C20 1 uF 1 2 3 CON3 C6 33 nF C7 33 nF C55 33 nF L1 33 nH G2 1 2 3 L24 1.2 nH L21 10 nH R6 9.1 k R4 20.0 k C2 33 nF Freq IF (MHz) 85 184 Freq LO (MHz) 965 1064 C3 (pF) 47 13 C5 (pF) 47 13 C35 (pF) DNI DNI R2 (k) 5.1 2.7 L11 (nH) 150 82 L6 (nH) 180 150 C22 (nF) 33 33 C17 (pF) 8 11 4 5 6 7 8 C3 3.9 pF 16 15 14 13 12 11 10 9 C35 R2 L11 L6 C22 VCC J4 CDMA IF J5 LO IN VCC1 P2-1 GND GND P2-2 P2-3 P2-4 P2 1 2 3 4 CON4 ENABLE TX BUF EN G1 G2
L17 2.2 nH
J1 CELL LNA IN
C4 33 nF
C5
C25 33 nF VCC J2 CELL LNA OUT
C17
L3 DNI C9 22.0 nH C8 1 pF C1 33 nF
G1
J3 CELL MIX IN
8-10
Rev A3 050902
RF2861
Evaluation Board Schematic CDMA450 Band
ENABLE TX BUFF ENABLE C46 33 nF C54 33 nF J6 LO OUT VCC P1 P1-1 + C20 1 uF 1 2 3 CON3 C6 33 nF C7 33 nF C55 33 nF L1 33 nH G2 L24 5.6 nH C25 33 nF VCC J2 CELL LNA OUT 2.7 pF R6 6.8 k R4 22 k C2 33 nF Freq IF (MHz) 85 Freq LO (MHz) 549 C3 (pF) 91 C5 (pF) 91 C35 (pF) DNI R2 (k) 6.8 L11 (nH) 68 L6 (nH) 270 C22 (nF) 33 C17 (pF) 27 L21 27 nH 1 2 3 4 5 6 7 8 C3 16 15 14 13 12 11 10 9 C35 R2 L11 L6 C22 VCC J4 CDMA IF J5 LO IN VCC1 P2-1 GND GND P2-2 P2-3 P2-4 P2 1 2 3 4 CON4 ENABLE TX BUF EN G1 G2
L17 2.2 nH
J1 CELL LNA IN
C4 33 nF
C5
C17
L3 33 nH
G1
C9 2.2 pF C8 DNI
C1 33 nF
J3 CELL MIX IN
Rev A3 050902
8-11
RF2861
IF Output Interface Network
Single-End IF Matching
C3 IF+ IF10 9 4 5
C1
IF+
VCC IF Saw 33 nF
L2
L1
R
C2
IF-
C1
L1, C1, C2, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to the following equation:
1 f IF = ----------------------------------------------------------L1 2 ----- ( C 1 + 2C 2 + C EQ ) 2
Where CEQ is the equivalent stray capacitance and capacitance looking into pins 9 and 10. An average value to use for CEQ is 2.5pF. R can then be used to set the output impedance according to the following equation:
1 1- -1 R = -------------------- - ----- 4 R OUT R P
where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1. C2 should first be set to 0 and C1 should be chosen as high as possible (not greater than 39pF), while maintaining an RP of L1 that allows for the desired ROUT. If the self-resonant frequencies of the selected C1 produce unsatisfactory linearity performance, their values may be reduced and compensated for by including C2 capacitor with a value chosen to maintain the desired FIF frequency. L2 and C3 serve dual purposes. L2 serves as an output bias choke, and C3 serves as a series DC block. In addition, L2 and C3 may be chosen to form an impedance matching network if the input impedance of the IF filter is not equal to ROUT. Otherwise, L2 is chosen to be large (suggested 120nH) and C3 is chosen to be large (suggested 22nF) if a DC path to ground is present in the IF filter, or omitted if the filter is DC-blocked.
8-12
Rev A3 050902
RF2861
Differential IF Matching
C2 IF Saw VCC IF+ IF10 9 4 5
IF+
L1
R
C1
IF-
L2 33 nF C2 L1
L1 and C1 are chosen to resonate at the desired IF frequency. C1 can be omitted and the value of L1 increased and utilized solely as a choke to provide VCC to the open-collector outputs, but it is strongly recommended that at least some small-valued C1 (a few pF) be retained for better mixer linearity performance. R is normally selected to match the input impedance of the IF filter. However, mixer performance can be modified by selecting an R value that is different from the IF filter input impedance, and inserting a conjugate matching network between the Resistive Output Network and the IF filter. C2 serve dual purposes. C2 serves as a series DC block when a DC path to ground is present in the IF filter. In addition, C2 may be chosen to improve the combine performance of the mixer and IF filter. L2 should choose to resonate with the internal capacitance of the SAW filter. Usually, SAW filter has some capacitance. Otherwise, L2 could be eliminated. A practical approach to obtain the differential matching is to tune the mixer to the correct load point for gain, IIP3, and NF using the single-end current combiner method. Second, use the component values found in the single-end approach as starting point for the differential matching. The two-shunt capacitors in the single-end could be converted in a parallel capacitor and the parallel inductor in the single-end need to be converted in two-choke inductor. Third, set the DC block capacitors (C2) in the differential-end matching to a high value (i.e., 100pF) and retune the resonate circuit (C1 & L1) and the resistor (R) for optimal performance. After optimal performance is achieved and if performance is not satisfactory, decrease the series capacitors until optimal performance is achieved.
Rev A3 050902
8-13
RF2861
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 1.50 (mm) Sq.
Dimensions in mm.
1.50 Typ. 0.50 Typ.
Pin 16
B
Pin 1
B
B
B
Pin 12
A 0.50 Typ. A C A A 0.55 Typ. B B B B
A A A A 0.75 Typ. 1.50 Typ.
Pin 8
0.55 Typ. 0.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
8-14
Rev A3 050902

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